Manrose timer fan circuit diagram?

[ebee]

Yes - I was think that I could not readily see a reason to disconnect one of the 4 gates even if not actually required "Two Heads are better than one" so two gates would be better than one, in theory - unless there was some problem if one could be a split second in front of the other on initial draw or somesuch and that`s the reason they decided to disconnect it but I could not reall envisage that as a viable reason but one of you might have had more idea than me.
The feeding inputs even if the outputs were not required was a well known habit I learnt years ago, probably completely OK for most stuff but a tadd safer practice to preseve the IC. (I have never actually met anybody whos hass worked on CMOS and blown the chip be not taking static precautions that are second nature in industry either but it is universally the disciplne).
Yes the floating inputs surprised me I admit but the non connection of gate d baffled me = if production line is set up one particular way it`s usually easier to carry on unless there is a real reason behind a change.
Just me being me!

 

[Harry Bloomfield]

The feeding inputs even if the outputs were not required was a well known habit I learnt years ago, probably completely OK for most stuff but a tadd safer practice to preseve the IC. (I have never actually met anybody whos hass worked on CMOS and blown the chip be not taking static precautions that are second nature in industry either but it is universally the disciplne).

Modern CMOS, has much better protected inputs, with regard to static discharge, than the early ones - didn't the later ones, include a suffix letter? I did manage to accidentally damage a few of the early ones. The reason to tie the inputs, up or down, was to ensure the didn't go into oscillation, if left open input, and indeterminate. I'm not clear, what such oscillation might do - maybe it affects the other gates on the chip, maybe it sets up noise on the supply lines?

 

[JohnW2]

Yes - I was think that I could not readily see a reason to disconnect one of the 4 gates even if not actually required "Two Heads are better than one" so two gates would be better than one, in theory - unless there was some problem if one could be a split second in front of the other on initial draw or somesuch and that`s the reason they decided to disconnect it but I could not reall envisage that as a viable reason but one of you might have had more idea than me.

As I've implied, I certainly have no idea.

The feeding inputs even if the outputs were not required was a well known habit I learnt years ago, probably completely OK for most stuff but a tadd safer practice to preseve the IC. (I have never actually met anybody whos hass worked on CMOS and blown the chip be not taking static precautions that are second nature in industry either but it is universally the disciplne).

I've been playing with CMOS ICs since the very earliest days (when they were theoretically more 'susceptible'), with few (usually no) 'anti-static precautions' and have never knowing damaged/killed one for that reason. What I did quite commonly 'blow up' back then were audio power ICs which did not have short-circuit protections of their outputs

Yes the floating inputs surprised me I admit but the non connection of gate d baffled me = if production line is set up one particular way it`s usually easier to carry on unless there is a real reason behind a change. ... Just me being me!

No, not just you. As you imply, someone must have thought there was some reason for the change (which seems to be in the 'less wise' direction) but goodness knows what that reason could have been!

 

[JohnW2]

Modern CMOS, has much better protected inputs, with regard to static discharge, than the early ones - didn't the later ones, include a suffix letter? I did manage to accidentally damage a few of the early ones.

As I've just written, it seems that I "got away with it", even with the earliest ones!

The reason to tie the inputs, up or down, was to ensure the didn't go into oscillation, if left open input, and indeterminate. I'm not clear, what such oscillation might do - maybe it affects the other gates on the chip, maybe it sets up noise on the supply lines?

Interesting question. Might it perhaps be to minimise power consumption? A CMOS gate which is 'doing nothing' (not changing state) consumes zero power. If it starts 'doing things' (like oscillating between states), it will continuously consume some power (albeit extremely little), increasingly so as the frequency of state-changing (e.g. 'oscillation') increases?

 

[ebee]

Yes I seem to remember the oscilations being the most mentioned of all.